Digital systems have signals with abrupt transitions and whose time variant analog behavior represents boolean (two-state logical) values described as ONE or ZERO, TRUE or FALSE, or perhaps HIGH or LOW. The ‘real’ information content carried by such signals is encoded within sequences or combinations of these logical values. Nevertheless, it will be remembered that when signals are sent from one place (component or assembly) to another, or from one entire system to another, they rely on their analog properties to do so. That is, it is their underlying voltage or current (or light) that makes the journey, while it is some observable property such as magnitude or polarity that is subsequently interpreted as representing one or the other of the possible logical values.
Very often it is the magnitude of a voltage that determines the logical value to be understood. The abrupt transitions are constrained to occur at particular times indicated by a clock signal, and the stable or asserted regions between transitions are compared against a threshold to ascertain the logical value. The nominal shortest period of time between transitions for a signal is called a UI (Unit Interval), and its phase and duration is either supplied by a clock signal accompanying the data, or is derived from the data.
Logic analyzers are members of a class of electronic test equipment that observes collections of digital signals, converts them to instances of corresponding logic values along a time axis, and reports on and analyzes their (logical) activity. This class of test equipment, which we may call data analysis equipment, generally samples only once within each consecutive UI, takes the sampled value as indicative of the logical value for that UI, and does not attempt to reconstruct the underlying analog waveform. A clock signal is either re-constructed from the data or is supplied as a separate signal, and transitions in the clock signal are used to delimit the UI. As the speeds of digital systems increase into the Gigabit per second region the issues of exactly where within the UI to make the threshold decision for a data signal, and with what threshold voltage, become increasingly problematic. Quite aside from how the SUT (System Under Test) itself performs these tasks, the logic analyzer has to perform them as well, and do so correctly if the measurement of the data is to have any utility. It is conventional for both the threshold and the delay relative to the onset of the UI (as indicated by a transition in the clock signal) to be adjustable by the operator of the logic analyzer. Hereinafter, we shall collectively refer to these as ‘sampling parameters’ and to their individual elements as ‘threshold’ and ‘sample position,’ respectively. Some logic analyzers even attempt to automate the process of selecting these sampling parameters. These prior art techniques for setting threshold and sample position each have certain associated disadvantages.
An eye diagram is a stylized representation of a signal's behavior. An eye diagram can be made by superimposing a large number of time domain trace segments that each correspond to just an individual UI (that's exactly how a ‘scope would make a basic eye diagram). Implicit in this idea is the notion that satisfaction of some clock signal-related trigger event allows the correct registration of each segment on the other. This will display both rising and falling edges, and asserted regions (whether HIGH or LOW) each in their same relative horizontal locations, for perhaps a million (or more) cycles of the signal. The result is (hopefully) a central empty opening called an ‘eye’ (on account of its shape) that is free of any traced activity, since during that time any signal will be either already HIGH or already LOW. At each edge of an eye for a typical (non-pulse) signal is an X-shaped boundary produced by rising and falling transitions, with straight lines above and below the Xs produced by the various consecutive ONEs and consecutive ZEROs in the data. And while it is then possible to discern if in that collection of cycles there were instances of overshoot, slow rise or fall times, or inappropriate asserted voltage levels, knowledge about which cycle(s) is(are) at fault is generally lost. That is a minor price to pay for an easily viewed presentation that gives valuable information about overall margins (the size and shape of the eye). Once any such violations of margins are confirmed, their location in the data (if such information is needed) and their causes can be sought using other test techniques. Often, two or three consecutive UIs are treated as a unit collection, and superimposed on other such unit collections to create an eye diagram having two or three eyes. There are other ways to actually create eye diagrams besides the brute force ‘scope technique alluded to above, and some of these are quite a bit faster than the ‘scope's method for the number of signal cycles that are typically of interest. They, too, incorporate the notion of triggering from a clock signal as the reference for registering events occurring at the same general location along the UI but measured during different cycles of the data.
For data analysis equipment, such as logic analyzers, that capture the logical values once per UI (as opposed to a ‘scope that densely samples the actual analog waveform), it is conventional to use the ‘X crossing’ voltage of an eye diagram as the threshold for a data receiver (comparator), and to delay the capture of the comparison output from the associated clock so as to locate the sample position midway between consecutive crossings. However, this may not actually be an optimum set of sampling parameters.
Recently, some data analysis equipment, including logic analyzers, have begun to support the ability to perform eye diagram measurements, and new techniques are thus possible within such test equipment (such as logic analyzers) to allow it to automatically recommend or decide the best time within the UI, and with what threshold, to ‘sample’ an incoming signal to decide its logical value. Such automatic selection (or a recommendation) should take the behavior of the data receiver into account and can be of benefit to the internal operation of the logic analyzer when used in its traditional logic analysis capacity (it is desirable that it not mis-sample the data . . . ). In addition, such recommended information (not necessarily obtained from a logic analyzer, but perhaps from a ‘scope that also does eye diagrams) can also be of use to persons responsible for setting the sampling parameters for the receivers that belong to/are part of the SUT itself, and that are not part of any external test equipment, such as logic analyzer.
Furthermore, the conventional notion that the best threshold voltage is at the ‘X’ crossing of an eye diagram, and that midway between the Xs is the best sample position, while often not a poor combination of choices, may not actually be the best combination. Another way to define the degree to which a combination of sampling parameters is satisfactory is to take into account certain performance requirements of the receiver that is in use, and choose a location that offers equal margins in all directions (i.e, for both directions in each of voltage and in time). This sounds harmless enough, but can be difficult to accurately visualize, particularly if the eye diagram for the signal of interest differs significantly from an ideal or nominally correct shape.
There are various reasons for this. Consider first the matter of threshold voltage. Unlike its brother the DSO (Digital Sampling Oscilloscope) that simply digitizes a waveform and reconstructs it afterward, the Logic Analyzer relies upon a threshold comparator (often called a ‘receiver’) to decide what the logic value is. So does the SUT. The behavior of the threshold comparator/receiver is of interest, and has an effect on margins. It is instructive to dwell on this topic for a moment.
Suppose that the threshold was one volt. Applied signals higher than one volt are reported as HIGH, while those less than one volt are reported as LOW. The threshold is supplied as an analog reference voltage, as we will assume that our one volt is as good as it gets (or at least a good as it needs to be), and remove it from consideration. However, we can ask certain embarrassing question, such as “Well, what happens if the reference voltage itself is applied to the data input?” It is a fair question, but one that ought never to happen as a steady state condition, since we expect the input signal to vary abruptly between two values on either side of that one volt. So, we might give an evasive answer, such as “Well, you get whatever logical output that you had before . . . .” The next question is: “Suppose an evil demon raised the input voltage to one tenth of a micro-volt above one volt. Then what?” At this point we confess the existence of hysteresis, and explain that it takes a rising signal going from LOW to HIGH an extra 100 mv above the threshold to cause a change in the receiver's output, and likewise another 100 mv below the threshold for falling transitions in the other direction. So we answer that there are two thresholds, 1.10V for rising signals and 0.900V for falling signals. Then we add that these numbers are exemplary only, and that they might not even be the same for the two directions of transition.
Question: “That is all well and good, but the demon is not so easily fooled. He raises the input from below 0.900 V to one micro-volt above 1.10V. Now what?”
Answer: “Maybe it'll switch, and maybe it won't. There is this noise floor . . . .”
Question: “I see. Then how about a millivolt above the upper threshold?”
Answer: “It'll probably switch, but it won't do so very quickly.”
Question: “Hmm, you mean that there is delay from when the input actually changes to when the output has the proper value?”
Answer: “Unfortunately, yes.”
Question: “Even if the one millivolt change had a really short rise time itself?”
Answer: “Probably so.”
Question: “This delay ends up in my measurement, and I don't like that. But I can live with it if it is well behaved, say, as a common mode effect that cancels out. I suppose then that falling signals have the same delay?”
Answer: “They have a delay, but it is generally not the same as for rising signals . . . .”
Question: “This is disgusting. I had no idea that comparators were so fussy. Suppose I supply more ΔV. Will that help?”
Answer: “Yes, especially if it has a respectable dv/dt to go with it.”
Question: “Alright, you've got me at a disadvantage. My real job is hunting demons, and I've got to get on with it. What's it going to take to get good performance?”
Answer: “Give us at least a nice snappy 250 mv and you are in business.”
Question: “That's rather pricey. Seems like a King's ransom. I suppose that for such a handsome effort there are essentially no delays?”
Answer: “No, there are still delays, but they are fairly short, and what is more, they are essentially equal for both rising and falling signals.”
Comment: “TWO HUNDRED AND FIFTY!?”
Reply: “Well, this IS a published specification for production parts in commerce. We have to keep the cost under control here, since we suspect that you are secretly building a Logic Analyzer and are not interested in just one signal, and that something like sixty-four channels is more likely to be the case. Probably most of the comparators will actually work well with half that specified value, but there is no guarantee . . . .”
This imaginary conversation could be repeated using the idea of a minimum pulse width that needs to be applied before the output will reliably switch from one state to the other. Half a nanosecond is a reasonable example value for minimum signal duration. So, when we consider where in an eye opening to locate sampling parameters for best Logic Analyzer operation (or more generally, for best operation of a particular data receiver in whatever kind of equipment) we ought to keep the minimum voltage excursion ΔVmin and its minimum duration ΔTmin in mind. Particularly so, if the shape of the eye opening for the applied signal is less than ideal.
Say, for example, the signals of interest arrive over transmission lines that are beset with reflections. This condition can give the eye opening a stepped contour, and to maximize the ability of the Logic Analyzer to sample correctly we may wish to deliberately move, say, the location of the sample position within the time duration of the UI. Or, perhaps the eye opening is not stepped, but is instead both sloped and not very high, or has ringing at one end. We may be tempted to slide the sample position over some to gain better access to the needed quarter of a volt or so change required by the comparator. The presence of jitter is another factor that affects the situation. But we realize that in changing the sample position we are trading increased voltage margin for a decrease in margin for pulse width. It is not so easy to tell by simple observation where the gain in one parameter's margin begins to erode the minimum margin needed for the other. This is particularly so if the eye diagram is for a pulse-type signal, or for a regular signal that has reflections, or, if for any kind of a clocked digital signal there are indicated signal occurrences for regions INTERIOR to the nominal eye opening (i.e, the signal violates the rule that the only time it is allowed to have a value between the asserted extremes is during a transition at the end/beginning of a UI, and that those transitions should be abrupt). This last business of signal activity indicated within the nominal eye opening, when combined with different rate of margin consumption versus changes in the sampling parameters, can REALLY complicate the task of finding suitable sampling parameters.
Thus, we see that there are various issues that can arise, and that should be taken into consideration if an automated mechanism is to be reliable in its recommendation or selection of an optimum set of sampling parameters, and is to avoid being flummoxed by various extreme signal behaviors. What to do?